TSMC’s 2-nanometer chipmaking process, known as N2, entered volume production in the fourth quarter of 2025, and by the company’s second-quarter 2026 earnings call it was already generating revenue and reshaping its finances. TSMC says N2 accounted for 3% of wafer revenue in the April-to-June quarter and is on track to dilute company-wide gross margin by 3 to 4 percentage points in the second half of 2026 as the ramp accelerates. Samsung, which announced its own 2nm mobile chip in December 2025, and Intel, which shipped its first 18A-based laptop chips in January 2026, are both racing to keep pace — with very different results so far.
What TSMC actually confirmed
TSMC’s own statement, issued as 2025 closed and reported by AFP, was direct: “TSMC’s 2nm (N2) technology has started volume production in 4Q25 as planned.” Production began at Fab 22 near Kaohsiung, with Fab 20 near Hsinchu following, according to reporting from Taipei Times and Tom’s Hardware. N2 is TSMC’s first process to use gate-all-around (GAA) nanosheet transistors, a structural change from the FinFET transistors used in every TSMC node back to 16nm. The company also introduced “super-high-performance metal-insulator-metal” capacitors, which it says roughly double capacitance density versus prior designs.
By the July 2026 earnings call, N2 was no longer just a lab milestone. CFO Wendell Huang told analysts the node’s ramp had pushed inventory days up to 87, and that gross margin guidance for the third quarter had dropped to 65-67% — down from a record 67.7% in Q2 — largely because of N2 start-up costs. CEO C.C. Wei described N2 as likely to be “a larger and longer-lasting node than 3 nanometer” for TSMC’s business.
Why 2 nanometers matters, in plain English
The “2nm” label doesn’t describe a literal transistor dimension anymore — it’s a marketing-era node name, as it has been for years across the industry. What actually changed is the transistor architecture. TSMC’s N2 replaces FinFETs, where current flows along the side of a fin-shaped silicon structure, with gate-all-around nanosheets, where the transistor gate wraps completely around a stack of thin silicon sheets. That gives engineers tighter control over current leakage and lets them tune transistor width more precisely for either speed or power efficiency.
The practical payoff, per TSMC’s own published comparisons against its N3E process: 10-15% faster performance at the same power draw, or 25-30% lower power consumption at the same speed, plus about a 15% increase in transistor density (up to 20% for logic-heavy designs). None of those are exotic claims by node-transition standards — they’re roughly in line with past TSMC generational jumps — but they matter because so much of the current AI buildout runs on power and thermal budgets, not raw transistor count alone.
Who’s actually buying these chips
TSMC has not published a customer list for N2, and Smashology found no on-the-record TSMC statement naming specific 2nm customers. What is confirmed: AFP’s December 2025 report on the production start named Nvidia and Apple as major TSMC clients generally, without specifying which chips of theirs use N2. More concretely, AMD CEO Lisa Su has confirmed the company’s Instinct MI450-series AI accelerators will use TSMC’s 2nm node, with the chips due in the second half of 2026 and OpenAI reported among the first customers to receive the hardware, according to Tom’s Hardware’s reporting on AMD’s own disclosures.
Notably, Nvidia’s next-generation Rubin GPUs are not on 2nm at launch. TrendForce reported in April 2026 that Rubin Ultra is sticking with a dual-die design built on TSMC’s 3nm family, meaning AMD is positioned to reach 2nm ahead of Nvidia in the AI-accelerator race — an unusual role reversal given Nvidia’s dominance in AI chip revenue.
On the smartphone side, Apple’s A20 and A20 Pro chips are widely reported — via MacRumors and other outlets citing supply-chain sources — to be Apple’s first 2nm chips, expected in iPhone 18 Pro models later in 2026. Apple has not confirmed this itself, so it should be read as informed industry reporting rather than a company announcement.
Samsung’s competing claim — and its asterisks
Samsung got to market with a public 2nm product announcement before TSMC’s customers did. On December 19, 2025, Samsung unveiled the Exynos 2600, which it called the industry’s first 2nm mobile application processor, built on its SF2 gate-all-around process (Samsung calls its version MBCFET). Samsung’s own performance claims: up to 39% higher CPU performance, 113% faster NPU throughput, and roughly double GPU performance with ray-tracing performance up 50%, per the company’s December announcement covered by TrendForce and other outlets.
But the rollout has been narrower than the headline suggests. Trade press citing South Korean outlet ZDNet Korea, as reported by AndroidHeadlines, put Exynos 2600 yield at around 50% as of January 2026 — up from a reported 37% months earlier, but still well below the 90%-plus yields mature nodes typically reach. The same reporting indicates Qualcomm’s Snapdragon chips, not Exynos, will still power the large majority of Galaxy S26 units sold globally, with Exynos concentrated in select European and Korean markets. Samsung itself has not published an official yield figure, so that number should be treated as trade-press reporting, not a confirmed company disclosure.
Intel’s 18A: a real product, a different race
Intel’s competing advanced node, 18A, is not directly comparable to TSMC N2 or Samsung SF2 on naming alone, but it’s the node Intel is using to argue it has closed the manufacturing gap. Intel’s own newsroom confirmed in January 2026 that Panther Lake — its first 18A-based processor family — launched as “the first AI PC platform built on 18A.” Panther Lake is a client-PC chip, not a smartphone or AI-datacenter part, so it doesn’t compete head-to-head with the same Apple, Nvidia, or AMD sockets that TSMC N2 is winning. Intel’s bigger strategic question — whether 18A can win meaningful external foundry customers beyond Intel’s own chips — remains unresolved in the reporting Smashology reviewed.
The price of being first
Being first to a new node is expensive, and TSMC is passing some of that along. DigiTimes has reported N2 wafer prices at roughly $30,000 per wafer — a level trade press has repeatedly flagged as a new industry high, though below the 50% price-hike figure that had circulated in earlier speculation. TSMC has not published official 2nm wafer pricing; the $30,000 figure comes from industry/supply-chain sourcing, not a company statement, and Smashology could not independently verify it.
What TSMC has confirmed on its own earnings call is the financial strain of the ramp: the 3-4 point gross margin dilution expected through the second half of 2026, and a raised 2026 capital expenditure guidance of $60-64 billion, up from a prior $52-56 billion range, with 70-80% of that spend going toward advanced-node capacity including N2. On July 16, 2026, TSMC also announced an additional $100 billion investment in Arizona — bringing its total announced U.S. commitment to $265 billion — for at least four more 2nm fabs and two advanced-packaging facilities, according to TSMC’s own announcement as reported by Tom’s Hardware and Data Center Dynamics.
What happens next
TSMC has said its enhanced N2P variant is scheduled for mass production in the second half of 2026, with Fab 20 and Fab 22 eventually supporting both N2P and the following A16 node later in the year. Trade press including Wccftech has reported that Qualcomm and MediaTek may move to N2P rather than base N2 for their next flagship mobile chips, positioned as a generational edge over Apple’s A20 — but this is sourced to supply-chain rumor reporting, not confirmed by Qualcomm, MediaTek, or TSMC, and should be read with appropriate caution. Samsung, meanwhile, has already begun promoting its second-generation SF2P process for 2027, targeting an Exynos 2700 successor and external customers, per TrendForce reporting on Samsung’s roadmap disclosures.
What Smashology verified
| Claim | Evidence reviewed | Assessment |
|---|---|---|
| TSMC began 2nm (N2) volume production in Q4 2025 | Direct TSMC statement via AFP wire report; corroborated by Taipei Times and Tom’s Hardware | Confirmed — company’s own words, multiple independent outlets |
| N2 offers 10-15% speed gain or 25-30% power reduction vs N3E | TSMC’s published technology comparison, cited by Tom’s Hardware and AFP reporting | Confirmed as TSMC’s own published figures; independent third-party benchmark verification not yet available |
| Samsung’s Exynos 2600 is the “world’s first 2nm mobile chip” | Samsung’s own December 2025 announcement, covered by TrendForce, MacRumors, AndroidAuthority | Confirmed as Samsung’s claim and product launch; “world’s first” is a marketing framing Samsung controls, not an independently audited title |
| N2 wafers cost roughly $30,000 each | DigiTimes trade-press report citing industry sourcing | Unconfirmed by TSMC directly — treat as credible trade-press reporting, not company-disclosed pricing |
| Apple’s A20/A20 Pro chips will use TSMC’s 2nm process | MacRumors and other outlets citing supply-chain sources; no Apple confirmation found | Plausible and widely reported, but unconfirmed by Apple — should be read as informed rumor until Apple’s own announcement |
Evidence limits and unresolved questions
- TSMC has not published a customer list for N2; the Nvidia/Apple linkage in early coverage was general context from a wire report, not a chip-specific confirmation.
- Samsung has not disclosed an official yield figure for Exynos 2600; the widely cited 50% figure traces to South Korean trade press relayed through secondary outlets, not a Samsung filing or statement.
- The reported $30,000-per-wafer N2 pricing is sourced entirely to trade press and industry channel checks; TSMC does not publish per-wafer pricing publicly.
- Whether Qualcomm and MediaTek will use N2P instead of base N2 for their next flagship mobile chips remains rumor-level, sourced to supply-chain reporting rather than statements from Qualcomm, MediaTek, or TSMC.
- Long-run 2nm yield rates for both TSMC and Samsung, and Intel 18A’s actual external-foundry customer wins, were not independently disclosed in any source reviewed and remain open questions heading into late 2026.
Sources
- TSMC: 2nm Technology overview
- AFP via Malay Mail: Taiwan’s TSMC starts mass production of ‘most advanced’ 2nm semiconductors
- Taipei Times: TSMC officially begins 2nm chip volume production in Q4 2025
- Tom’s Hardware: TSMC begins quietly volume production of 2nm-class chips
- Investing.com: TSMC (TSM) Q2 2026 earnings call transcript
- Tom’s Hardware: TSMC commits another $100 billion to Arizona for at least four more 2nm fabs
- Data Center Dynamics: TSMC announces additional $100bn investment in Arizona as chipmaker posts $40.2bn revenue for Q2 2026
- DigiTimes: At $30,000 a wafer, TSMC’s 2nm push still draws a rush of customers
- Tom’s Hardware: AMD’s Lisa Su confirms next-gen GPUs are 2nm, beating Nvidia’s upcoming Vera Rubin
- TrendForce: Nvidia’s Rubin Ultra Seen Sticking to Dual-Die Design on Packaging Constraints; TSMC 3nm Demand Intact
- TrendForce: Samsung Unveils Exynos 2600: Industry-First 2nm GAA AP With 113% AI Performance Uplift
- MacRumors: Samsung Announces World’s First 2nm Mobile Chip Ahead of Apple
- TechInsights: Samsung Exynos 2600 (2nm SF2) Process Analysis
- AndroidHeadlines: Samsung Hits 50% Yield for 2nm Exynos 2600 Chip, But Is It Enough?
- Intel Newsroom: Intel Unveils Panther Lake Architecture: First AI PC Platform Built on 18A
- MacRumors: A20 and A20 Pro Chips (2nm) Expected to Debut in These iPhone Models
- Wccftech: Qualcomm and MediaTek Reportedly Eyeing an Advantage Over Apple by Moving to TSMC’s Improved 2nm N2P Process
Method note: Smashology built this report by prioritizing direct statements from TSMC, Samsung, and Intel — earnings calls, newsroom releases, and technology pages — over secondhand summaries, and by cross-checking every wire-service claim against at least one independent trade outlet. Where a figure or product tie-in traces only to supply-chain or trade-press sourcing rather than a company’s own disclosure, it is labeled as reported rather than confirmed, and flagged again in the Evidence limits section above. No figures, dates, or quotations in this piece were generated or estimated; each traces to a specific source listed above.
Edin Pula
Edin Pula is the editor responsible for reviewing and publishing content at Smashology Media. He oversees sourcing, fact-checking, corrections, and editorial standards across coverage of internet culture, technology, entertainment, news, and crime.